In some integrated circuits, for example those which utilize analog-to-digital converters, the sample-and-hold device is often a critical part. If the sample-and-hold device has a capacitive storage device for holding a sample, on the one hand, the charging time of the capacitive storage device limits the possible clock frequency (cycles of sample phase and hold phase per time) of the analog-to-digital converter and, on the other hand, residual charge from a previous sampling may still be present in the capacitive storage device, which leads to errors in the course of the analog-to-digital conversion. If the residual charge depends on a digital-to-analog conversion to be carried out, so-called intersymbol interference occurs. Such errors occur in particular in the case of analog-to-digital converter architectures in which a value determined in a manner dependent on the analog-to-digital conversion of the sample is added to or subtracted from the sample, as is carried out for example in pipeline architecture and two-step flash architecture.
It is therefore desirable to provide a sample-and-hold device in which the influence of a preceding cycle on a subsequent cycle can be reduced, minimized, or eliminated.